This invention relates to an arithmetic unit for an electronic computer of the microprogram-controlled type, and more particularly to an arithmetic constant generating means.
In an electronic computing system, the instructions to control sub-units, such as registers, counters, adders etc., gates interconnecting the sub-units with one another, and functional units interconnecting the gates to provide proper timing signals are called the micro instructions, and the micro-programming refers to the definition of a larger function through programming such micro instructions in a synthetic manner.
Micro instructions are classified into two types: the horizontal micro instruction and the vertical one. In a horizontal micro instruction, each bit of the micro instruction corresponds directly to a control signal; while with a vertical micro instruction, numerous control signals are produced through the various combinations of the individual bits of the micro instruction.
FIG. 1 shows a schematic construction of a conventional computer using a horizontal microprogram and FIG. 2 shows a schematic construction of a conventional computer using a vertical micro program.
In FIG. 1, the control storage CS comprises a control matrix 11 and a sequence matrix 12, each matrix serving as a coder. When an instruction code 102 serving as a part of a micro instruction, produced by the sequence matrix 12, is sent through a delay circuit 8 to an address register 4, the instruction code 102 is decoded by a decoder 9 to select an address. The reading operation on the control storage CS is performed through the selective application of clock pulses CL thereto and accordingly a specified signal, i.e. a micro order specifying signal 101 serving as a part of a micro instruction, is read out from the control matrix 11. The number of the total signals 101 available from the matrix is equal to that of the micro orders used in the computer in question. The signals 101 control the operations of an arithmetic circuit 2, registers 6 of different functions, a local storage 7 etc. At the same time when the micro order specifying signal 101 is read out of the control matrix 11, an instruction code 102 is read out from the sequence matrix 12. The delivered instruction code 102 is sent through the delay circuit 8 to the address register 4 and renews the content of the address register 4 so that an address for the micro instruction to be effected on the basis of the following clock pulses CL is specified.
The horizontal (or direct-control) microprogram as shown in FIG. 1, in which one bit in the control storage CS corresponds to one micro order, is used for the computer which requires a simplified decoder logic, especially a large-capacity computer since this method can decrease the machine cycle time to a great extent.
In FIG. 2, on the other hand, a single micro instruction read out of the control storage CS to a micro instruction register 10, is divided into plural fields SFo-SFn and they are converted to different codes through combinations of exclusive micro orders.
The vertical (or coding-control type) micro-program as shown in FIG. 2 is used for a computer in which the number of the bits to be controlled needs to be decreased to decrease the cost preferentially, that is, especially for a small-capacity machine having a simple structure. According to this method, there is required additional time for decoding, which results in an increase in the processing time.
Thus, the horizontal micro-programming system is used mainly for a large-scale computer and the decoder logic used there is simplified so that high speed control is possible by increasing the wordlength of each micro instruction. On the other hand, the cost can be reduced at the sacrifice of processing speed by decreasing the wordlength.
Incidentally, there is a rather high necessity of an arithmetic constant being generated, in the firmware or the like, but only a low necessity of the same sort for a set of instructions according to the standard specification.
For this reason, control fields as a part of a micro instruction are usually used to generate such arithmetic constants.
Moreover, in the generation of the arithmetic constant in a conventional computer using the horizontal micro-program, an arithmetic constant having a large number of digits is generated in several steps.
FIG. 3 shows in block diagram a main part of a conventional arithmetic unit and FIG. 4 shows a micro-program for commanding the generation of an arithmetic constant, used in the arithmetic unit shown in FIG. 3.
For example, in the case where such a calculation as given by the following expression is performed by a conventional apparatus: EQU (UO)=RG+(012345).sub.16 ( 1),
a group of micro instructions such as shown in FIG. 4 are sequentially read out from the control storage CS and set in a micro instruction register 10 in FIG. 3. In the above expression (1), (UO) indicates a specified area in a local storage 70 in FIG. 3, RG the content of one of a plurality of registers 60, and (012345).sub.16 an arithmetic constant in the hexadecimal notation.
The micro instruction register 10 is divided into an arithmetic control section 110 and a sequence control section 120. The respective bits of the arithmetic control section are used to compile micro order specifying signals for various controls, just as described with FIG. 1, and the sequence control section 120 produces a content to specify the next address in the control storage CS. Namely, the content of the sequence control section 120 of the micro instruction register 10 is sent to a micro instruction address generating circuit 20, which delivers a micro instruction address. After the micro instruction address has been set in a control storage address register 40, the next micro instruction is read out from the location in the control storage corresponding to the above set micro instruction address and then set in the micro instruction register 10.
Here, if the micro instruction had a long wordlength, a field for an arithmetic constant, or a constant field for short, could be independently defined, but since the computer in question has a simple constitution as mentioned before and since the control storage CS and the micro instruction register 10 cannot treat signals having long wordlengths, then the constant field 14 is formed by overlapping parts of the arithmetic control section 110 and the sequence control section 120.
By using this constant field 14, the micro instructions as shown in FIG. 4 are sequentially set in the micro instruction register 10. First, according to a micro instruction a.sub.1, the content (01) of the constant field 14 is stored, through an arithmetic circuit, in the area UO in the local storage 70 and then according to a micro instruction a.sub.2, the content (23) is stored in the same area UO. Finally, according to a micro instruction a.sub.3, the content (45) is also stored in the same area UO. Thus, an arithmetic constant (012345).sub.16 is stored in the area UO of the local storage 70 according to the three micro instructions a.sub.1 -a.sub.3.
Next, according to a micro instruction a.sub.4, the micro order specifying signal generated from the arithmetic control section 110 causes the content of the area UO of the local storage 70 and the content of the register RG of the register group 60 to be sent to the arithmetic circuit 2. The arithmetic circuit 2 produces the sum of the contents and the sum is stored in the area UO of the local storage 70.
As described above, with the arithmetic unit shown in FIG. 3, the arithmetic circuit 2 is occupied three times to produce the constant (012345).sub.16 and therefore three arithmetic cycles are needed for the generation of an arithmetic constant. Therefore, whenever the micro instruction step is entered, a degradation in performance is inevitable.
Since the micro-program, unlike a usual program (set of micro instructions) directly control the operations of the sub-units, it may be regarded as a part of hardware, but it may often be caused to belong to an independent class called firmware, having an intermediate property.
It is necessary especially in firmware to generate arithmetic constants during an arithmetic operation. They may be, for example, self-evident operand addresses or self-evident operands (constants). Since the firmware is executed by replacing the function of software by a micro-program, the performance in calculation operation must necessarily be improved. In that case, however, if a time of several machine cycles is required to generate an arithmetic constant, the loss in performance is considerable.
It is of course possible to eliminate this problem by causing each micro instruction to have a wordlength long enough to produce a large arithmetic constant, but in this case the storage capacity of the control storage CS must be increased, which leads to a considerable increase in the cost.
It is also possible to prevent the cost from increasing by using most of the fields for the generation of arithmetic constants without increasing the wordlength of every micro instruction, but in this case, too, the function of the arithmetic control section 110 will be restricted or the function of the sequence control section 120, e.g. address branching, will be limited.
To eliminate such a limitation, a full cycle must be used for the generation of an arithmetic constant. This, however, leads to a degradation in performance.